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74LVT16374 * 74LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs
January 1999 Revised June 2002
74LVT16374 * 74LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The LVT16374 and LVTH16374 contain sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. The LVTH16374 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These flip-flops are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16374 and LVTH16374 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16374), also available without bushold feature (74LVT16374) s Live insertion/extraction permitted s Power Up/Power Down high impedance provides glitch-free bus loading s Outputs source/sink -32 mA/+64 mA s Functionally compatible with the 74 series 16374 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number 74LVT16374G (Note 1)(Note 2) 74LVT16374MEA (Note 2) 74LVT16374MTD (Note 2) 74LVTH16374G (Note 1)(Note 2) 74LVTH16374MEA (Note 2) 74LVTH16374MTD (Note 2) Package Number BGA54A (Preliminary) MS48A MTD48 BGA54A MS48A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: Ordering code "G" indicates Trays. Note 2: Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
(c) 2002 Fairchild Semiconductor Corporation
DS012022
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74LVT16374 * 74LVTH16374
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Pin Names OEn CPn I0-I15 O0-O15 NC Description Output Enable Input (Active LOW) Clock Pulse Input Inputs 3-STATE Outputs No Connect
FBGA Pin Assignments
1 A B C D E F G H J O0 O2 O4 O6 O8 O10 O12 O14 O15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VCC GND GND GND VCC NC OE2 4 CP1 NC VCC GND GND GND VCC NC CP2 5 NC I1 I3 I5 I7 I9 I11 I13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15
Truth Tables
Inputs Pin Assignment for FBGA CP1 Outputs I0-I7 H L X X O0-O7 H L Oo Z Outputs I8-I15 H L X X O8-O15 H L Oo Z OE1 L L L H Inputs CP2

L X

L X
OE2 L L L H
(Top Thru View)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance Oo = Previous Oo before HIGH to LOW of CP
Functional Description
The LVT16374 and LVTH16374 consist of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops.
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74LVT16374 * 74LVTH16374
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays.
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74LVT16374 * 74LVTH16374
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in High or Low State (Note 4) VI < GND VO < GND VO > VCC VO > VCC Output at High State Output at Low State V mA mA mA mA mA
-0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50
64 128
64 128 -65 to +150
C
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage High-Level Output Current Low-Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA
-32
64
-40
0
85 10
C
ns/V
t/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) (Note 5) II(OD) (Note 5) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH IOZH+ Power Off Leakage Current Power Up/Down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Bushold Input Minimum Drive 3.0 3.0 3.6 3.6 3.6 0 0-1.5V 3.6 3.6 3.6 75 -75 500 -500 10 1 -5 1 100 100 -5 5 10 A A A A A A VCC - 0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 A A V V 2.0 0.8 T A = -40C to +85C Min Max -1.2 V V II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 64 mA VI = 0.8V VI = 2.0V (Note 6) (Note 7) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND or VCC VO = 0.5V VO = 3.0V VCC < VO 5.5V Units Conditions
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74LVT16374 * 74LVTH16374
DC Electrical Characteristics
Symbol ICCH ICCL ICCZ ICCZ+ ICC Parameter Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 8)
Note 5: Applies to bushold versions only (74LVTH16374).
(Continued)
VCC (V) 3.6 3.6 3.6 3.6 3.6 T A = -40C to +85C Min Max 0.19 5 0.19 0.19 0.2 mA mA mA mA mA Outputs HIGH Outputs LOW Outputs Disabled VCC V O 5.5V, Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND
Units
Conditions
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 9)
TA = 25C Min Typ 0.8 -0.8 Max Units V V Conditions CL = 50 pF, RL = 500 (Note 10) (Note 10)
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA = -40C to +85C, CL = 50 pF, RL = 500 Symbol Parameter VCC = 3.3V 0.3V Min fMAX tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW tOSHL tOSLH Setup Time Hold Time Pulse Width Output to Output Skew (Note 11) Output Disable Time Maximum Clock Frequency Propagation Delay CP to On Output Enable Time 160 1.9 1.6 1.3 1.0 1.5 2.0 1.8 0.8 3.0 1.0 1.0 4.3 4.5 4.4 4.5 4.6 5.0 Max Min 160 1.9 1.6 1.3 1.0 1.5 2.0 2.0 0.1 3.0 1.0 1.0 4.6 5.2 5.0 5.4 4.8 5.4 VCC = 2.7V Max MHz ns ns ns ns ns ns ns Units
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 12)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VCC = Open, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74LVT16374 * 74LVTH16374
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A
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74LVT16374 * 74LVTH16374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74LVT16374 * 74LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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